ADT7476A
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60
Table 77. REGISTER 0x73 CONFIGURATION REGISTER 2 (POWER-ON DEFAULT = 0x00) (Note 1)
Bit No.
Mnemonic
R/W
Description
0
FanPresDT
R/W
When FanPresenceDT = 1, the state of Bits [3:1] of 0x73 reflects the presence of a 4-wire fan
on the appropriate TACH channel.
1
Fan1Detect
Read-only
Fan1Detect = 1 indicates that a 4-wire fan is connected to the TACH1 input.
2
Fan2Detect
Read-only
Fan2Detect = 1 indicates that a 4-wire fan is connected to the TACH2 input.
3
Fan3Detect
Read-only
Fan3Detect = 1 indicates that a 4-wire fan is connected to the TACH3 input.
4
AVG
R/W
AVG = 1 indicates that averaging on the temperature and voltage measurements is turned
off. This allows measurements on each channel to be made much faster (x16).
5
ATTN
R/W
ATTN = 1 indicates that the ADT7476A removes the attenuators from the +2.5 V
IN
, V
CCP
,
+5.0 V
IN
, and +12 V
IN
inputs. These inputs can be used for other functions such as
connecting up external sensors. It is also possible to remove attenuators from individual
channels using Bits [7:4] of Configuration Register 4 (0x7D).
6
CONV
R/W
CONV = 1 indicates that the ADT7476A is put into a single-channel ADC conversion mode.
In this mode, the ADT7476A can be made to read continuously from one input only, for
example, Remote 1 temperature. The appropriate ADC channel is selected by writing to
Bits [7:5] of TACH1 minimum high byte register (0x55).
Bits [7:5], Register 0x55
000
2.5 V
001
V
CCP
010
V
CC
(3.3 V)
011
5.0 V
100
12 V
101
Remote 1 Temperature
110
Local Temperature
111
Remote 2 Temperature
7
Res
This bit is reserved and should not be changed.
1. This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register have no effect.
Table 78. REGISTER 0x74 INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT [7:0] = 0x00)
Bit No.
Mnemonic
R/W
Description
[0]
2.5 V/
THERM
R/W
2.5 V/THERM
= 1 masks SMBALERT
for out-of-limit conditions on the 2.5 V/THERM
timer
channel.
[1]
V
CCP
R/W
V
CCP
= 1 masks SMBALERT
for out-of-limit conditions on the V
CCP
channel.
[2]
V
CC
R/W
V
CC
= 1 masks SMBALERT
for out-of-limit conditions on the V
CC
channel.
[3]
5.0 V
R/W
5.0 V = 1 masks SMBALERT
for out-of-limit conditions on the 5.0 V channel.
[4]
R1T
R/W
R1T = 1 masks SMBALERT
for out-of-limit conditions on the Remote 1 temperature channel.
[5]
LT
R/W
LT = 1 masks SMBALERT
for out-of-limit conditions on the local temperature channel.
[6]
R2T
R/W
R2T = 1 masks SMBALERT
for out-of-limit conditions on the Remote 2 temperature channel.
[7]
OOL
R/W
OOL = 0 when one or more alerts are generated in Interrupt Status Register 2, assuming all
the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT
is still asserted.
OOL = 1 when one or more alerts are generated in Interrupt Status Register 2, assuming all
the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT
is not asserted.
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